Enhance scheduling/optimization for ops before register write or a pipe stage

The following is a common pattern in DSLX code

```
A = if (condition) { B } else { A };
```

XLS generally converts this to a select and scheduled with the timing expected of the mux. However, if A's only users are the next state or a pipeline register, after hardware synthesis, the cost of this is minimized as the condition can be directly fed to the register enable of the flops we generally use.

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Likewise if A is an array that is registered either as the next state or a pipeline register, the following code
```
A = if (condition) ( update(A, index, val) } else { A }
```
is converted by XLS to an array update followed by a select. In this case, (again if A has no users other than next state or a pipeline register) XLS overestimates the cost of the operation twicefold. After hardware synthesis would be minimal due to the folding of the select into the flop.

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The optimizer could also be enhanced to prefer this structure -- preferring to pull selects before state updates or flops to take advantage of being able to place logic within flops. Preferring to generate structure amenable to use of combo-flops is an extension to this idea.