Channels: Need a way to represent several ports guarded by a single ready/valid

For example, consider an AXI slave interface, which has (among others) the read transaction ports ARADDR, ARSIZE, ARLEN, and ARBURST, all protected by the pair ARVALID and ARREADY. I could write this as a channel whose payload is {ARADDR, ARSIZE, ARLEN, and ARBURST}, who would be guarded by ARVALID and ARREADY, but AIUI, that's not trivially mappable to the port declaration:
```
module foo (
input logic [31:0] araddr,
input logic [2:0] arsize,
input logic [7:0] arlen,
input logic [1:0] arburst,
output logic arready,
input logic arvalid
)
```

It'd instead map to
```
typedef struct packed {
input logic [31:0] araddr;
input logic [2:0] arsize;
input logic [7:0] arlen;
input logic [1:0] arburst;
} axi_struct_t;

module foo (
input axi_struct_t data,
output logic arready,
input logic arvalid
)
```

I'm not sure how one would wire this up with other [System]Verilog modules - maybe it's not an issue? Maybe it is?