Add metadata describing pipeline registers

Consumers of XLS verilog might benefit from knowing which registers correspond to which pipeline stage. Example uses include computing a per-stage critical-path delay for synthesis results. This metadata could be emitted as part of the module signature (or related proto) which is generated in the codegen pipeline.

Also, internally in the codegen piepline, it may be useful to know the pipeline registers as well. We attempt to reconstruct this information when generating Verilog at the end of the pipeline here:

https://github.com/google/xls/blob/961b764a5f4b7cd83a9bd137fa2d979fbcfdddd9/xls/codegen/block_generator.cc#L139

This enables us to emit the verilog in a stage by stage fashion for readability. We know this pipeline information at the start of codegen when the schedule is applied and the block is created but we throw it away. Perhaps we should keep that information around in some form. Perhaps as part of the IR. Registers in blocks (`reg foo(...)`) could be optionally declared as part of a particular stage. Later mutations to registers (e.g., adding a reset signal) would preserve this stage information. An alternative would be to have it stored outside the IR and perhaps passed along the codegen pipeline as a separate data structure in CodegenPassUnit:

https://github.com/google/xls/blob/961b764a5f4b7cd83a9bd137fa2d979fbcfdddd9/xls/codegen/codegen_pass.h#L43

However that seems more error prone.

cc @nanavati