simulators should have an option to support SystemVerilog

It seems that the iverilog invocation doesn't allow for SystemVerilog support:
https://github.com/google/xls/blob/c330e64365e56439ab9496159aa8664c6cd5eb6a/xls/simulation/simulators/iverilog_simulator.cc#L42
Which could cause simulation to fails with verilog generated by `codegen_main` by default (since `use_system_verilog` default to true):
https://github.com/google/xls/blob/6d593b81ff45ae6fdf15d2fea68bdd5da253200b/xls/tools/codegen_main.cc#L109
```
/tmp/xls_tempfile_Xzkpj6:34: syntax error
/tmp/xls_tempfile_Xzkpj6:34: error: Invalid module instantiation
/tmp/xls_tempfile_Xzkpj6:36: error: Invalid module instantiation
/tmp/xls_tempfile_Xzkpj6:38: error: invalid module item.
```

It would be nice if a similar option was available on the `VerilogSimulator` interface (also defaulting to `true`!); according to `iverilog` documentation system verilog can be enabled with the following `-g` option:
https://iverilog.fandom.com/wiki/Iverilog_Flags#-g.3Cgeneration_flag.3E