Emit selects using case

We currently emit selects using a chain of ternary operators. Example:
```
foo = sel(s, cases={a, b, c, d})
```
is emitted as:
```
assign foo = s == 0 ? a : (s == 1 ? b : (s == 2 ? c : d));
```

For readability and potentially qor (avoids inferring a priority encoder) it may be better to emit as a case statement in an always block. Example:

```
case (s)
0 : foo = a;
1 : foo = b;
2 : foo = c;
3 : foo = d;
endcase
```

Also supports default easily:

```
case (s)
0 : foo = a;
1 : foo = b;
default : foo = c;
endcase
```

And SystemVerilog supports a `unique` specifier which tells the synthesis tool that only one case can be true which potentially avoids a chain of muxes (though the tool can likely figure this out?).

Two-way selects can likely remain as a ternary expression.