Avoid special handling of widthless wire/reg declaration in VAST
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codegen
- Dominant language
- C++
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Description
In VAST we currently special cast single bit reg/wires when defining and indexing:
https://github.com/google/xls/blob/05ccc3b54a7b359fdc12963d064f3ee02aa6a30c/xls/codegen/vast.cc#L349
https://github.com/google/xls/blob/05ccc3b54a7b359fdc12963d064f3ee02aa6a30c/xls/codegen/vast.cc#L553
This produces:
```
wire foo;
```
instead of:
```
wire [0:0] foo;
```
and avoids invalid indexing of a widthless (single bit) wire/reg. However, it would be cleaner and less surprising if VAST didn't magically do this transformation under the hood. This belongs at a higher abstraction level such as modulebuilder.
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