Verilog codegen for tuple outputs should retain their structure

I have a DSLX function that returns a tuple of type `(u1, u8)`. The tuple fields are called `(result, state)`. I would expect the emitted verilog to look like this:

```
output wire result,
output wire [7:0] state
```

Instead, I get a packed bit vector called `output wire [8:0] out`.

This is still usable, but generally it would be easier to integrate the generated code if the fields were unpacked into separate output ports.