[codegen] `codegen_main` crashes on procs with multi-token carried state

observed this when playing around with things, filing for completeness

**Describe the bug**
`codegen_main` crashes with an internal error when a proc's carried state contains more than one `token`, even for a minimal proc that only sends on a single output channel and carries the second token unused.

The proc converts to IR successfully, but codegen fails with:

```text
INTERNAL: XLS_RET_CHECK failure (xls/codegen/block_conversion.cc:271) ...
UNIMPLEMENTED: Proc has zero-width state element 0, but type is not token or empty tuple, instead got ().
```

**To Reproduce**
Steps to reproduce the behavior:

1. Put the following in `multi_token_state_codegen_bug.x`:

```dslx
proc MultiTokenState {
out_ch: chan out;

config(out_ch: chan out) {
(out_ch,)
}

init { (token(), token()) }

next(state: (token, token)) {
let active_tok = send(state.0, out_ch, u1:1);
(active_tok, state.1)
}
}
```

2. Convert to IR:

```sh
"${XLSYNTH_TOOLS}/ir_converter_main" \
multi_token_state_codegen_bug.x \
--top=MultiTokenState \
--dslx_path . \
--dslx_stdlib_path "${XLSYNTH_TOOLS}/xls/dslx/stdlib" \
--type_inference_v2 \
--output_file=multi_token_state_codegen_bug.ir
```

3. Run codegen without reset:

```sh
"${XLSYNTH_TOOLS}/codegen_main" \
multi_token_state_codegen_bug.ir \
--top=__multi_token_state_codegen_bug__MultiTokenState_0_next \
--generator=pipeline \
--pipeline_stages=1 \
--clock_period_ps=1000 \
--delay_model=unit \
--use_system_verilog \
--worst_case_throughput=1 \
--output_verilog_path=multi_token_state_codegen_bug.sv
```

4. See internal error:

```text
INTERNAL: XLS_RET_CHECK failure (xls/codegen/block_conversion.cc:271) ...
UNIMPLEMENTED: Proc has zero-width state element 0, but type is not token or empty tuple, instead got ().
```

5. The same failure also reproduces with reset enabled:

```sh
"${XLSYNTH_TOOLS}/codegen_main" \
multi_token_state_codegen_bug.ir \
--top=__multi_token_state_codegen_bug__MultiTokenState_0_next \
--generator=pipeline \
--pipeline_stages=1 \
--clock_period_ps=1000 \
--delay_model=unit \
--use_system_verilog \
--worst_case_throughput=1 \
--reset=rst \
--output_verilog_path=multi_token_state_codegen_bug_reset.sv
```

**Expected behavior**
No `XLS_RET_CHECK` failure.