Document the sequential generator usage / build rule

XLS can generate IR into a module via the pipeline generator, combinational generator, or sequential generator. Sequential generator does the (perhaps one would consider "traditional") time multiplexing of "virtual program counter" states among a set of resources, registers, and interconnect (which we might think of as "reconfigurable-VLIW style") for a given latency L and pops out a single result after that latency.

This functionality lives in the repo but I don't think it's documented or generally exposed at the moment, we should make a point of doing this and making this mode easily accessible.