Multi-ported write regfile-like structure timing characterization script
Open
delay model
enhancement
- Dominant language
- C++
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- Avg merge
- 2d 10h
- Merged PRs (30d)
- 135
Description
We've been shmooing timing on a multi-ported register-file-looking structure in terms of number of entries, number of write ports, and bitwidth -- this issue tracks that we can make this part of our timing characterization flow so it can be re-used / re-evaluated on different target processes.
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