Multi-port write register-file-like structure characterization

This issue tracks a client implementation (of the synthesis server) that checks the timing closure for a register-file-like structure that has N write ports. In general the sweep space is N entries, B bits wide, W write ports, and I believe we currently want to assume we can take all of the values out (broadside) on a given clock. Initial values are something like N=80 B=22 W=4 but we can scale that down for unit testing purposes.