[enhancement] Add DSLX and/or IR source annotations to generated Verilog

### What's hard to do? (limit 100 words)

It’s hard to match generated Verilog code back to the original DSLX source. DSLX code is turned into an intermediate representation and optimized before Verilog is made. Because of this, the Verilog often looks very different from the DSLX it came from. This makes it tough to debug code when the generated design does not match the expected behavior.

### Current best alternative workaround (limit 100 words)

Right now, people have to reason about the parts of the DSLX code that matches with the generated Verilog by tracking similarities between operations and generated variable names.

### Your view of the "best case XLS enhancement" (limit 100 words)

XLS could keep track of where each piece of DSLX code came from and add this info as comments in the generated Verilog, like in the following example:
```verilog
// From my_file.x: myProc, line 42, col 5
assign nor_359453 = ~(____state_0 | wr_resp_valid_reg | rd_resp_valid_inv);
// From my_file.x: myProc, line 43, col 5
assign and_359454 = and_359447 & wr_req_valid;
// From my_file.x: myProc, line 44, col 5
assign and_359455 = and_359447 & ~wr_req_valid & rd_req_valid;

```