[enhancement] Name legalization should choose keywords based on configuration

### What's hard to do? (limit 100 words)

You might want to do any of the following:
- Generate Verilog but avoid all SystemVerilog keywords b/c the file will be used in multiple contexts
- Generate SystemVerilog that avoids keywords in other standards, e.g. Verilog-AMS
- Choose specific versions of standards that need to allow future keywords for compatibility reasons

Name legalization currently chooses its set of keywords entirely based on what kind of RTL is being generated, so these things aren't possible.

### Current best alternative workaround (limit 100 words)

Hack name legalization to do what you want or post-process the RTL.

### Your view of the "best case XLS enhancement" (limit 100 words)

A separate codegen flag specifying which standards' keywords to avoid.