[enhancement] channel slicing

### What's hard to do? (limit 100 words)

Currently it's hard to synchronise N procs communication on channels of size `T` (example: 4x `chan`) w/ 1 proc (ex: 4x `chan`) on a single channel of wider size `N*T` (ex: 1x `chan`).

### Current best alternative workaround (limit 100 words)

This require creating an intermediate proc that `join` receive operation from multiple narrow channels before concatenating the result and send it to a wider channel.

```
proc Merger {
a: chan in;
b: chan in;
c: chan in;
d: chan in;
e: chan out;

init { () }

config(a: chan in, b: chan in, c: chan in, d: chan in, e: chan out) {
(a, b, c, d, e)
}

next(state: ()) {
let tok = join();
let (tok_a, data_a) = recv(tok, a);
let (tok_b, data_b) = recv(tok, b);
let (tok_c, data_c) = recv(tok, c);
let (tok_d, data_d) = recv(tok, d);
let tok_e = join(tok_a, tok_b, tok_c, tok_d);
send(tok_e, e, data_a ++ data_b ++ data_c ++ data_d);
}
}
```

Resulting in redundant `rdy` `vld` signal pairs synchronisation handshake for each of the procs.

```
module user_module(
input wire clk,
input wire [31:0] user_module__a_data,
input wire user_module__a_valid,
input wire [31:0] user_module__b_data,
input wire user_module__b_valid,
input wire [31:0] user_module__c_data,
input wire user_module__c_valid,
input wire [31:0] user_module__d_data,
input wire user_module__d_valid,
input wire reset,
input wire user_module__e_ready,
output wire [127:0] user_module__e_data,
output wire user_module__e_valid,
output wire user_module__a_ready,
output wire user_module__b_ready,
output wire user_module__c_ready,
output wire user_module__d_ready
);
wire p0_all_active_inputs_valid;
wire p0_stage_done;
assign p0_all_active_inputs_valid = user_module__a_valid & user_module__b_valid & user_module__c_valid & user_module__d_valid;
assign p0_stage_done = p0_all_active_inputs_valid & user_module__e_ready;
assign user_module__e_data = {user_module__a_data, user_module__b_data, user_module__c_data, user_module__d_data};
assign user_module__e_valid = p0_all_active_inputs_valid;
assign user_module__a_ready = p0_stage_done;
assign user_module__b_ready = p0_stage_done;
assign user_module__c_ready = p0_stage_done;
assign user_module__d_ready = p0_stage_done;
endmodule
```

### Your view of the "best case XLS enhancement" (limit 100 words)

Similar to way scalar can already be [sliced](https://google.github.io/xls/dslx_reference/#bit-slice-expressions) in DSLX, in would be nice to be able to slice wide channels in narrower channels pair that share the same `rdy` `vld` signal pairs.

```
config() {
let (s, r) = chan("some_chan");
let (a, b, c, d) = (s[0:32], s[32:64], s[64, 96], s[96,128]);
spawn another_proc(a);
spawn another_proc(b);
spawn another_proc(c);
spawn another_proc(d);
}
```