[enhancement] Add support for common bus interfaces (AXI, Wishbone, TileLink)

### What's hard to do? (limit 100 words)

Currently, interfacing DSLX designs with common communication buses (AXI, Wishbone, TileLink) is not possible. Adding support for these buses, along with logic for storing data in Control and Status Registers (CSR), would enable easier integration with other designs, especially those with a CPU. This would provide a more convenient interface for modifying design behavior and reporting errors.

### Current best alternative workaround (limit 100 words)

Currently, one has to provide their own Verilog wrapper that will be responsible for handling bus transactions and sending the data to the generated XLS design.

### Your view of the "best case XLS enhancement" (limit 100 words)

There might be different options to handle this problem, here are two possibilities:

1. A mechanism similar to RAM rewriting, utilizing predefined DSLX structures with all the necessary information required to perform transactions on the given bus. These structures would then be translated into appropriate bus signals in Verilog during the code generation.

2. An additional library of Verilog cores/templates designed for specific buses, which would convert bus-specific transactions into one or more stream-like interfaces used by XLS procs.

In the future, a [sequential FFI feature](https://github.com/google/xls/issues/1301) could be used together with the second option to provide more convenient experience for interfacing with the external Verilog.