FFI: Implement simulator-based quickcheck and tests

To use FFI functions, it is crucial that the DSLX implementation matches the external implementation.

Within DSLX, we'd use `[#quickcheck]` or `[#test]` functions to test expectations of functional behavior.

The external implementations are not XLS, so can't be simulated using the JIT or interpreter. But there are a simulators for Verilog available which we can be utilize to provide testing for these. Generate code or some in-memory JIT for these Verilog modules (should be pluggable; possibly one of Verilator, Yosys cxxrtl, iverilog, ...) and then wire them up to be able to interface with _our_ XLS interpreter/JIT calling into these simulated implementations to provide `#[test]` and `#[quickcheck]` functionality.