[enhancement] add option to convert assert IR nodes into async-fatal-signal hardware

### What's hard to do? (limit 100 words)

Right now `fail!`/`assert!` in the DSL only become assert ops in the IR that turn into Verilog/SV assertions. On some chips there are async fatal signals that a block can propagate. A useful transform could be to identify assertion nodes in the IR and turn them into async fatal hardware automatically.

### Current best alternative workaround (limit 100 words)

Currently users could create an explicit fatal signal as output using the same predicates they use in assertion operations.

### Your view of the "best case XLS enhancement" (limit 100 words)

Having the option to transform the assert IR operations automatically for either "all assert ops" or "some identified subset of assert ops" in the design.