A demo for IR to netlist LEC
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Description
Readme of solver says: _That Verilog is then compiled by an external tool, which, if successful, will output a "netlist" - a set of standard cells (think AND, OR, NOT, flops, etc.) and wires connecting them that realizes the design_
is there an example show how to convert a verilog file generated by codegen_main to netlist that can be consumed by lec solver?
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