Verilog output: Emit constant values only once, ideally as localparam

Looking at Verilog output, the same constant is proliferated and assigned to wires in slightly different names.

Here an example from the apfloat.x adder; there is one constant ...

```rust
const MAX_EXPONENT = std::mask_bits();
```

... which then shows up in the generated verilog multiple times (here the output of a grep that only contains these values:)

```verilog
wire [7:0] p1_MAX_EXPONENT_comb;
wire [7:0] p1_MAX_EXPONENT__5_comb;
wire [7:0] p1_MAX_EXPONENT__7_comb;
wire [7:0] p1_MAX_EXPONENT__8_comb;
wire [7:0] p1_MAX_EXPONENT__6_comb;
assign p1_MAX_EXPONENT_comb = 8'hff;
assign p1_MAX_EXPONENT__5_comb = 8'hff;
assign p1_MAX_EXPONENT__7_comb = 8'hff;
assign p1_MAX_EXPONENT__8_comb = 8'hff;
assign p1_MAX_EXPONENT__6_comb = 8'hff;
```

### Expected
Ideally, these would be emitted only _once_ as a readable constant and possibly as `localparam` of sorts.