Error with RAM rewriting of nested Procs that access the same RAM

I encountered an error while attempting to generate Verilog code from the Proc that issues some of the RAM accesses from the child Proc. I was able to successfully generate Verilog code from a flat Proc with equivalent logic. I suspect that this may be a bug in the RAM rewriting step, given that the error message I received was related to this step:
```
INFO: From Building Verilog file: bazel-out/k8-fastbuild/bin/xls/examples/nested_proc_ram_example.v:
E0108 09:39:46.310099 3 ram_rewrite_pass.cc:59] INTERNAL: XLS_RET_CHECK failure (xls/codegen/ram_rewrite_pass.cc:59) channel->GetDataPortName().has_value() data port not found- channel ram_bug__req_s should be streaming with ready/valid flow control.
0x557ff501e450: xabsl::StatusBuilder::CreateStatusAndConditionallyLog()
0x557ff3b23ce9: absl::lts_20230802::StatusOr<>::StatusOr<>()
0x557ff3b23a5f: xls::verilog::(anonymous namespace)::GetStreamingChannel()
0x557ff3b22d8e: xls::verilog::(anonymous namespace)::GetReqBlockPorts()
0x557ff3b181a5: xls::verilog::(anonymous namespace)::Ram1RWRewrite()
0x557ff3b252a8: std::__1::__function::__func<>::operator()()
0x557ff3b17d1f: xls::verilog::RamRewritePass::RunInternal()
0x557ff3b0dbde: xls::PassBase<>::Run()
0x557ff3b0eb08: xls::CompoundPassBase<>::RunNested()
0x557ff3b0e282: xls::CompoundPassBase<>::RunInternal()
0x557ff3b0dbde: xls::PassBase<>::Run()
0x557ff3b0ac4b: xls::verilog::ToPipelineModuleText()
0x557ff3afda2f: xls::ScheduleAndCodegen()
0x557ff3aad404: (anonymous namespace)::RealMain()
0x557ff3aacfc7: main
0x7fbff7fee083: __libc_start_main
```

I pushed my code to the [antmicro/xls/53470-ram-bug](https://github.com/antmicro/xls/tree/53470-ram-bug). You can observe that the Verilog code can be generated out of the flat design using:
```
bazel build --verbose_failures //xls/examples:ram_bug_single_proc_ram_example_verilog
```
The error occurs when enerating the code from a nested Proc using:
```
bazel build --verbose_failures //xls/examples:ram_bug_nested_proc_ram_example_verilog
```