DSLX Output Verilog: Breaking of a Wire to Tuple Having No use

From example 9 of [Learning-Notebook](https://colab.corp.google.com/drive/1yr5csc5FWX-qdVeQmqkvFpB0u_c2fFEI?resourcekey=0-m-_nXR58_tvK_kycuHXRAg#scrollTo=XPW-7SlZFD8g) :
```
assign sum_with_carry = {1'h0, product__1} + {1'h0, ____state};
assign __statearry_bit = sum_with_carry[8];
assign sum = sum_with_carry[7:0];
assign __user_module__output_data_buf = {__statearry_bit, sum};
```

In the above example there is no use of breaking sum_with_carry into `__statearry_bit`, and `sum` as these 2 variables are anyways not used anywhere else in the code. It can be directly used as: `assign __user_module__output_data_buf = sum_with_carry;`