DSLX Output Verilog: Inefficient Declaration of Constant

```
wire [8:0] __user_module__output_data_reg_init;
assign __user_module__output_data_reg_init = {1'h0, 8'h00};

always_ff @ (posedge clk) begin
if (reset) begin
__user_module__output_data_reg <= __user_module__output_data_reg_init;
end
```

In the above example, the constant wire __user_module__output_data_reg_init is declared which is not getting updated anywhere else in the piece of code. (From example 9 of [Learning-Notebook](https://colab.corp.google.com/drive/1yr5csc5FWX-qdVeQmqkvFpB0u_c2fFEI?resourcekey=0-m-_nXR58_tvK_kycuHXRAg#scrollTo=XPW-7SlZFD8g))

Moreover, since reset anyways implies reset of the system so we can directly assign 0 to the register instead of using additional wire.