Implement DSLX DMA

# DSLX DMA

This is an umbrella issue to track implementation of the DSLX DMA.

## Motivation

Decoders/encoders (RLE, Zstd), security hash functions (SHA), error detection and correction function (CRC) are amongst most commonly developed modules in DSLX. In broader terms, they can be characterized as hardware accelerators, which operate on streams of data. In order to provide a common environment for as many applications as possible, it is desired to build a generic acceleration interface. This goal will be achieved by implementing a Direct Memory Access module.

## Architecture

The DMA module will:
- read and write data to system memory over AXI interface
- push and pop data from the accelerator over AXI-Stream interface
- be controlled by writes and reads from CSRs, available from the AXI interface
- use an interrupt pin to signal job completion or errors
- take after [the FastVDMA project](https://github.com/antmicro/fastvdma), a similar project, but implemented in Chisel