Codegen (block generator) should emit a comment before emitting logic for trace nodes ($display)

Currently with pipelined codegen, the emitted Verilog is nicely broken into stages with comments like:
```
// ===== Pipe stage 3:
...

// Registers for pipe stage 3:
...
```
However, the final dump of trace nodes gets lumped in with the registers for the final stage:
```
// Registers for pipe stage 3:
reg [31:0] p3_tuple_6543;
always_ff @ (posedge clk) begin
p3_tuple_6543 <= p3_tuple_6543_comb;
end
assign out = p3_tuple_6543;
always @ (posedge clk) begin
if (p1_not_6299_comb) begin
$display("debug:x= format{s: %d, b: %d, f: %d}", p1_x_s__13_comb, p1_x_b__29_comb, p1_x_f__13_comb);
end
end
always @ (posedge clk) begin
if (p1_not_6299_comb) begin
$display("debug:max_e = %d", p1_max_e_comb);
end
end
...
```
It would help readability to insert a space and comment.