Determined Pipeline Length and Idle Stages

I'm attempting to operate a design at a higher frequency by using pipelining. However, despite my efforts, the system appears to allocate everything to a single stage.

Error Message:
INVALID_ARGUMENT: Unable to reach the desired pipeline length. Consider using --pipeline_stages=18.

Interestingly, while --pipeline_stages=18 does work, all operations are still funneled into the initial stage. For comparison, --pipeline_stages=1 produces the same result. Additionally, setting --clock_period_ps=500000 introduces 17 idle stages, indicating potential underlying issues.

This odd behavior could be a consequence of a recent update: [GitHub Commit](https://github.com/google/xls/commit/657dc81a24953d25ae63307e2fdff7b9f9d678d6).

codegen_main \
run_design_proc_opt.TXT \
--generator pipeline --delay_model="asap7" \
--output_signature_path=run_design.sig.textproto \
--output_schedule_path=run_design.sched.textproto \
--flop_inputs=false \
--flop_outputs=false \
--clock_period_ps=5000 \
--output_schedule_ir_path=output.sched.ir \
--output_block_ir_path=output.block.ir \
$RESET_COMMAND \
--top=run_design_proc --use_system_verilog=false --output_verilog_path=run_design.sv

For reference, see the detailed design here: [run_design_proc_opt.TXT](https://github.com/google/xls/files/12440992/run_design_proc_opt.TXT)

Thanks!