Support ram latency =/= 1 in codegen
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enhancement
ram
- Dominant language
- C++
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Description
RAM configurations allow latency to be specified and are treated as scheduling constraints, but the codegen pass currently implicitly assumes latency==1.
Latency==0 is a special case because of how sends/receives are ordered within a stage (I think receives must all fire before any sends, which for a memory means the receive cannot fire based on the send or else it will deadlock).
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