RISC-V devicetree "riscv,isa" comment is no longer accurate

[The comment about RISC-V devicetree extension order](https://github.com/google/cpu_features/blame/main/src/impl_riscv_linux.c#L25) is not aligned with the URL in the comment.

This is mea culpa, because I initially got it wrong & came back and changed it.
In your comment, the order is `^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$`
The pattern was changed to `^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$` which is more complicated than it was before, because the first multiletter extension doesn't have to have the leading _, *sigh*.

Per my commit message, v (vector) was also resorted slightly and p (packed-simd) & j (dynamic languages) were added.
I don't think the re-order has any impact for you as you don't look for any of v, k, h or p - but allowing people to omit the leading may impact your acquisition of zicsr and zifencei.

On that note though, "riscv,isa" can't be used to tell whether zicsr/zifencei are present in the cpu.
Unfortunately, as they used to be part of i, there's no way of telling if a devicetree containing "i" also contains zicsr/zifencei.
Sure, if they're in the "riscv,isa" string, then they are there but if they're not in the string they may still be in the hardware :)