Investigate the current state of Auto-vectorization for RISC-V targets

- [x] Compiling [TSVC](https://github.com/UoB-HPC/TSVC_2) benchmark would be a good way to find out if commonly found loop structures are getting vectorized.
- [ ] Instruction scheduling of vectorized loops. If there is no instruction scheduling for RISC-V vectors, then we might have to create a separate task for this.
- [x] Eliminate redundant vsetvl instructions. If we are not doing it already, a simple reaching definition analysis should accomplish this.