Synthesizing the model

Hi @tcal-x and @alanvgreen
I am fairly new to the hardware design and synthesis world. I am working on the pdti8 model project. I have implemented few custom cfu instructions in verilog. The renode emulation is working correctly. Now I want to synthesize this project to see the number of LUTs FFs and routing netlist. How do I do this? I couldn't find concrete steps/process for this on the documentation page.