Use of L2 in FPGA setups

Hi @alanvgreen and @tcal-x ,
**I would appreciate it if you could clarify a simple question** I need to be answered soon, since I have a deadline:
What is the use of the L2 cache in the CFU framework especially on FPGA setups, since as I understand it is inherently the same memory structure as L1 in the device level - ie, single cycle BRAM units. So, does it make sense to have an L2 in the hierarchy or is there some inherently different memory arch. used that consumes lesser resources for L2 per byte.
Thanks,
Bala.