L2 cache parameter description (sub 1KB)

Hi @tcal-x and @mithro ,
I wanted to know if Litex just removes the L2 cache (ie, 0K) when we use a value of lower than 1024 bytes. Since, Ive noticed that when I put in a very low size like 64B , during liftoff, L2 is shown as 0. Also, in the digilent_arty.py file L2 size is mentioned as some_number*1024 . So, I mainly wanted to know if this is true for all values < 1KB and if it is 0, does this mean there is a direct connection between L1 I and D-cache with DDR memory?
OR
Does it just display 0K on liftoff, when it actually uses the said memory?
_**Please let me know about this soon**_
Thanks,
Bala.