Flexibility in modifying i and d-cache configs.

Hi @tcal-x and @mithro ,
I was trying to change certain parameters of the d-cache on the Vexriscv using the scala file ([](https://github.com/google/CFU-Playground/blob/main/soc/vexriscv/src/main/scala/vexriscv/GenCoreDefault.scala)). From the parameters, I can gather that in a given 'way'( or column ) there _has_ to be 4096 bytes ( looking at the formula for number of ways written in terms of dcache/ icache size). Is there any way to change this? Because it could be useful to see finer granularity in changes of d-cache size to observe performance benefits. As of now, I think we can only increment the size in multiples of 4096 bytes.

On another note, is there any way to change L2 cache parameters as well, and is it a common L2 cache or separate for Imem and dmem.

Please let me know about this soon,
Thanks,
Bala.