Verilator simulation dumps 'sim.vcd'; it should dump 'sim.fst'

We set up Verilator simulation (`make PLATFORM=sim load`) to dump FST format traces.

https://github.com/google/CFU-Playground/search?q=fst

However, something changed and now we dump `sim.vcd`. Perhaps LiteX changed the name of an arg.

To reproduce,
```
cd proj/proj_template_v
make PLATFORM=sim load
```
At menu, hit "t" for trace then "Q" for quit to produce a minimal waveform file.

The tracefile will be in `$CFUROOT/soc/build/sim.proj_template_v/gateware/`. You'll see `sim.vcd` instead of `sim.fst`.