google / google/CFU-Playground
VexRiscv configuration with iCache alone hangs (SFL related)
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- Verilog
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Description
The following Vexriscv configuration hangs when you try to run on the board:
`generate+bypass:false+csrPluginConfig:mcycle+dCacheSize:0+hardwareDiv:false+iCacheSize:8192+mulDiv:false+prediction:none+safe:false+singleCycleMulDiv:false+singleCycleShift:false`
It is all CPU params set to false/zero except for `iCacheSize` set to 8192.
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