google / google/CFU-Playground
Accuracy of perf_get_mcycle() and perf_get_mcycle64() using Arty a7 100T board
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- Verilog
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Description
Hi @tcal-x ,
I've tried to profile some cfu-function calls for my accel. design and as well as for a "test-setup". I'm seeing some unusually high cycle times. For ex:- Using the basic template cfu.v file:
```
// Trivial handshaking for a combinational CFU
assign rsp_valid = cmd_valid;
assign cmd_ready = rsp_ready;
//
// select output -- note that we're not fully decoding the 3 function_id bits
//
assign rsp_payload_outputs_0 = cmd_payload_function_id[0] ?
cmd_payload_inputs_1 :
cmd_payload_inputs_0 ;
```
And using the "test-setup" code in the header file:
```
/*Single cycle cfu test*/
int start_cfu_comb = perf_get_mcycle();
int test_3 = cfu_op1(0,1,2);
int test_4 = cfu_op0(2,1,2);
int test_5 = cfu_op1(1,3,4);
int test_6 = cfu_op0(0,4,5);
int end_cfu_comb = perf_get_mcycle();
printf("test_3 %d\n", test_3); //Exp: 2
printf("test_4 %d\n", test_4); //Exp: 1
printf("test_5 %d\n", test_5); //Exp: 4
printf("test_6 %d\n", test_6); //Exp: 4
printf("Time taken (perf ) %d\n", end_cfu_comb- start_cfu_comb);
//Breaker
while(1==1);
printf("Done\n");
```
When running the above and profiling via perf_get_mcycle ( or mcycle 64) on the Arty a7 100T board @ 70 MHz clk rate, I'm getting cycle times around 180 (mcycle64()) and 92(mcycle()) for the above setup. It should ideally be around 4-6 cycles, so is there any issue with perf_get_mcycle() or mcycle64() ?
I'l try using custom counters in the cfu file to check it as well.
Please let me know soon.
Thanks,
Bala.
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