Usage of fpga DRAM in synthesis

Hi @tcal-x ,
I had a general doubt regarding synthesis of the Vexriscv core with the accelerator peripheral designed on an fpga.
Are the memory resources used in synthesis restricted to flip flops, BRAM, registers, and all single cycle access elements on the fpga OR is DRAM also used by default?
Do we need to write our own memory interface IPs to access DRAM/ off chip memory or is this done by default using vivado?

Essentially, I want my setup to have multi cycle memory accesses when running on an fpga, so that upon more data reuse in buffers, I see performance benefits( because I avoid these high latency accesses)
Thanks,
Bala.