Latest VexRiscv CFU interaction is hanging

When bumping VexRiscv and pre-generated verilog to recent master, we saw hangs using the CFU using either locally generated verilog files, or those generated upstream. Original discussion here: https://github.com/google/CFU-Playground/pull/592#issuecomment-1136534363. @davidlattimore had found the commit that seemed to cause the issue: https://github.com/SpinalHDL/VexRiscv/commit/b2e61caf9e62d8febe59eaf654856edec73e5412

Further investigation shows that it seems to be due to a new "en" register, initialized `false`, accessed as bit 31 of a csr, used here:
https://github.com/SpinalHDL/VexRiscv/commit/b2e61caf9e62d8febe59eaf654856edec73e5412#diff-0c3bf8c460b84c679bb5ae6755da7da8487141f0ffb5cadcc76d8775e024d169R184

If I start with a new verilog that exhibits the hanging, and then hand-modify all initialization and modification of verilog register `CfuPlugin_en` so that it is only set to 1'b1, then the hanging behavior goes away.

I suspect that we just need to write `true` to this CSR bit during software initialization.

However, this exposed a gap in our CI testing -- we have no tests of the VexRiscv / CfuPlugin RTL. We need to add one or more tests before closing this issue.