Basys3 board with Vivado gives error - memory region `main_ram' not declared

I am trying the process given at https://cfu-playground.readthedocs.io/en/latest/setup-guide.html with Basys3 board and Vivado 2021.2. Just adding TARGET=digilent_basys3 during make.

During "make load" I am getting the error - "memory region `main_ram' not declared."

Do I need to make some changes in ./third_party/python/litex_boards/litex_boards/targets/digilent_basys3.py?

Referring to https://github.com/google/CFU-Playground/issues/492 seems like to need to put some value for "integrated_main_ram_size" but not sure how much would actually work for liftoff.

Tried integrated_main_ram_size = 0xFFFFF, but gives some errors -

ERROR: [DRC UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 512 of such cell types but only 100 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
ERROR: [DRC UTLZ-1] Resource utilization: RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 256 of such cell types but only 50 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
ERROR: [DRC UTLZ-1] Resource utilization: RAMB36E1 over-utilized in Top Level Design (This design requires more RAMB36E1 cells than are available in the target device. This design requires 256 of such cell types but only 50 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.

Is this because the demo code larger than memory and some other smaller code might work?

Start with the setup guide and reproduce `make load` for `TARGET=digilent_basys3`. Inspect `third_party/python/litex_boards/litex_boards/targets/digilent_basys3.py`, then compare the `integrated_main_ram_size` setting with the reported `main_ram` and Vivado utilization errors. Done means the Basys3 build loads without the missing-region error or exceeding available RAM resources.

Written by the indexing model from the issue text.