google / google/CFU-Playground
verilator sim with mport dual port arena
Open
- Dominant language
- Verilog
- Stars
- 565
- Forks
- 160
- PR merge metrics
- No merged PRs in 30d
Description
For debugging gateware/software integration problems, it would be useful to be able to verilate a SoC with dual port memory in its separate arena.
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