VexRiscV - SlimoptCfu does not appear to be working

I have a minimal Cfu and with SlimOptCfu on HPS Proto2, the result appears to be always wrong:

```
/* Generated by Yosys 0.12+13 (git sha1 21fbdb663, clang 11.1.0-4+build2 -fPIC -Os) */

(* \nmigen.hierarchy = "Cfu" *)
(* top = 1 *)
(* generator = "nMigen" *)
module Cfu(cmd_ready, cmd_payload_function_id, cmd_payload_inputs_0, cmd_payload_inputs_1, rsp_valid, rsp_ready, rsp_payload_outputs_0, reset, port0_addr, port1_addr, port2_addr, port3_addr, port0_din, port1_din, port2_din, port3_din, clk, rst, cmd_valid);
reg \$auto$verilog_backend.cc:2083:dump_module$2 = 0;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:182" *)
input [9:0] cmd_payload_function_id;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:184" *)
input [31:0] cmd_payload_inputs_0;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:185" *)
input [31:0] cmd_payload_inputs_1;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:181" *)
output cmd_ready;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:180" *)
input cmd_valid;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/proj/hps_accel/gateware/gen2/hps_cfu.py:32" *)
reg f = 1'h0;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/proj/hps_accel/gateware/gen2/hps_cfu.py:32" *)
reg \f$next ;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:190" *)
input [31:0] port0_addr;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:191" *)
input [31:0] port0_din;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:190" *)
input [31:0] port1_addr;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:191" *)
input [31:0] port1_din;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:190" *)
input [31:0] port2_addr;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:191" *)
input [31:0] port2_din;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:190" *)
input [31:0] port3_addr;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:191" *)
input [31:0] port3_din;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:189" *)
input reset;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:188" *)
output [31:0] rsp_payload_outputs_0;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:187" *)
input rsp_ready;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/python/nmigen_cfu/cfu.py:186" *)
output rsp_valid;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
always @(posedge clk)
f <= \f$next ;
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
\f$next = 1'h1;
(* src = "/usr/local/google/home/avg/src/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f$next = 1'h0;
endcase
end
assign rsp_valid = 1'h1;
assign rsp_payload_outputs_0 = 32'd305419896;
assign cmd_ready = 1'h1;
endmodule
```

Every result received by the CPU is 0x13355779

This was the nmigen used to generate the Cfu.

```
from nmigen import Signal
from nmigen_cfu import CfuBase

from .constants import Constants

class Cfu(CfuBase):
"""Gen2 accelerator CFU.

Assumes working with a slimopt+cfu VexRiscV, which rsp_ready is always true.
"""
def elab(self, m):
# for now, everything completes in a single cycle, so can be always ready
m.d.comb += self.cmd_ready.eq(1)

m.d.comb += self.rsp_out.eq(0x12345678)
m.d.comb += self.rsp_valid.eq(1)

f = Signal()
m.d.sync += f.eq(1)

def make_cfu():
return Cfu()
```

The 'f' signal exists to ensure that a clk signal is generated.

I haven't had time to isolate the bug better yet, but the above failing code is available at https://github.com/alanvgreen/CFU-Playground/blob/slimopt-bug/proj/hps_accel/gateware/gen2/hps_cfu.py