google / google/CFU-Playground

Vivado timing check is not done for Arty

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Verilog
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Description

If I build for Arty, like this:

```
make PLATFORM=common_soc TARGET=digilent_arty bitstream
```

the timing check for Vivado is not done. Timing failures are ignored. I really want them to be reported instead.

The Makefiles do the timing check when `USE_VIVADO` is defined. The problem is that Litex will use Vivado by default for Arty (and other boards using Xilinx parts I guess), even though `USE_VIVADO` is not explicitly defined. The timing check is needed in those cases too.

This is only a problem for Vivado. For nextpnr, timing failures are indicated with a non-zero exit status. For Radiant, Litex checks the logs itself. It's only Vivado where we have to check the logs ourselves in the Makefile.

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