Investigate DIV behaviour after a speed switch
Open
research
- Dominant language
- Markdown
- Stars
- 783
- Forks
- 134
- Avg merge
- 6h 54m
- Merged PRs (30d)
- 3
Description
FF04 - DIV - Divider Register (R/W)
This register is incremented at rate of 16384Hz (~16779Hz on SGB). Writing any value to this register resets it to $00. Additionally, this register is reset when executing the stop instruction, and only begins ticking again once stop mode is exited. This also occurs during a speed switch. (**TODO: how is it affected by the wait after a speed switch?**)
Contributor guide
Assessment
This issue has not been assessed yet.