GBC-only hardware regs do not differentiate {Non-,}CGB Mode

Turns out GBC-exclusive registers (or specific bits thereof, like bit 1 of `SC`) are either available on GBC hardware the entire time, or locked in DMG compat mode (and this can be by them being read-only, or being read-write but having no effect!)

We do not document this at all—in particular, it turns out that the table relying on Mooneye's `boot_hwio-C` is documenting Non-CGB Mode, leaving any CGB Mode differences undocumented. (Plus I've found out that the test ROM accesses BG palette data regs sometimes during Mode 3, so maybe a few of its values are incorrect..? >_<) Note that documenting this is also useful to developers, since Non-CGB Mode *does* have a few differences from DMG/SGB, such as the STAT write bug or bit 0 of LCDC; so it is useful to highlight a way to distinguish them.

Preferably, this data could be fished up from somewhere and submitted either here or in a draft PR, while we debate the following question.

How should that be presented? Part of why this hasn't been documented thus far is that there is very little appetite for treating Non-CGB Mode specially, which is fair; thus I would be inclined to not present this information inline, but rather in a dedicated table (whether that's as a new page or a sub-section of the existing GBC page can be thought about later).

Start with the existing table based on Mooneye's boot_hwio-C and the current GBC documentation. Research and compare the documented Non-CGB and CGB-mode behavior of the affected registers, including the BG palette timing concern, then propose a dedicated table or subsection that makes the differences clear.

Written by the indexing model from the issue text.