Explain why PPU modes 0-3 are numbered that way

https://gbdev.io/pandocs/Rendering.html#ppu-modes describes modes 0 to 3 (0 = hblank, 1 = vblank, 2 = OAM scan, 3 = drawing pixels). It's not immediately obvious why the four phases of rendering are numbered this way, especially since reading from top-left to bottom-right counts "2, 3, 0, 1". If someone's already familiar with the SNES and its `BGMODE` register, they might be used to referencing these modes by number, but the Pan Docs page is not making it clear.

As @ISSOtm pointed out to me, the $FF41 `STAT` register's lowest two bits indicate the PPU mode, as per https://gbdev.io/pandocs/STAT.html. However, that page could also be more clear: saying that it "indicates the PPU’s current status" says nothing about *how*.

I think both STAT.html and Rendering.html could briefly note the connection between each other, so that the numbered modes would clearly have a point. (If the Pan Docs typically refer to hardware.inc constants, those have 0-3 `STAT_HBLANK/VBLANK/OAM/LCD` values which could be listed.)

Start with Rendering.html#ppu-modes and STAT.html, then check the referenced $FF41 STAT register details and the hardware.inc STAT_HBLANK/VBLANK/OAM/LCD values. Done when both pages clearly connect STAT bits 0–1 and the numbered 0–3 modes to the four rendering phases.

Written by the indexing model from the issue text.