Document that SB can be written after SC

My original comment from Discord

> This is actually safe. There's a clock generator for the serial hardware unit that's fed by the 16384 Hz tap of DIV and divides it by 2 to create 8192 Hz. This divider is reset every time SC is written. And the first pulse that shifts bits happens next negative edge of the output of the divider. So you have like 63-127 M cycles from writing SC, depending on the current phase of DIV.

https://raw.githubusercontent.com/furrtek/DMG-CPU-Inside/master/Schematics/6_SERIAL_LINK.png

Todo: test and verify that emulators and for that matter real hardware actually handle it like it appears from the DMG-CPU-inside schematic.