Document STAT interrupt oddities

> \ Mode 2 works differently in terms of interrupts because it's only checked at a single, specific M-cycle
> \ Meaning, enabling Mode 2 interrupt during Mode 2 will not trigger an interrupt
> \ and similarly, mode 2 cannot block interrupts
> \ So enabling the LYC interrupt during mode 2 can trigger an interrupt even if Mode 2's interrupt is already enabled
> \ Also, wasn't LY=LYC immune to being blocked by Mode 0 due to some delay?
> \ I think there's something like that but I'd have to check SameBoy's source

Start by checking SameBoy's source, which the discussion identifies as the place to verify the STAT interrupt behavior. Document the confirmed Mode 2 and LY=LYC interrupt oddities in the pandocs reference, with the work complete when those cases are accurately described.

Written by the indexing model from the issue text.