Anyone experienced in deploying (quantizing & compiling) SlowFast on Xilinx-FPGA with Vitis AI?

Hello,

I want to deploy the SLOWFAST_8x8_R50 on a SoC FPGA (Xilinx Zync Ultrascale+). Therefore I use the Xilinx-Framework Vitis AI 2.0. I successfully quantized and compiled a resnet50 model which runs on the FPGA. But now I'am struggeling with the quantization of the SlowFast network. Has anyone already tried to deploy SlowFast on Xilinx FPGA?

Many thanks!