f4pga / f4pga/prjxray

tilegrid: automatically generate number of frames

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enhancement
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Python
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Description

Currently tilegrid code hard codes the number of frames a tile uses. However, this information is known after partgen in run. We should automatically read this from the part json (or equivalent yaml) file.

The following locations have hard coded entries:
- add_tdb.py: see tdb_fns
- generate_full.py:db_add_bits(): see "entry = {"

Prioritize add_tdb.py as the code in generate_full.py might get phased out in favor of add_tdb.py.

Sample tilegrid entry showing "frames: 36":
```
"CLBLL_L_X12Y135": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00020600",
"frames": 36,
"height": 2,
"offset": 71,
"words": 2
}
```

Roughly corresponds to this information in the part .json (the 36 part):

```
"global_clock_regions": {
"top": {
"rows": {
"0": {
"configuration_buses": {
"CLB_IO_CLK": {
"configuration_columns": {
...
"2": {
"frame_count": 36
},
"3": {
"frame_count": 36
},
```

For details on how to do this transformation, see "Frame Address Register" on page 110: https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

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