Add option to bit2fasm to skip emitting empty CLE sites
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enhancement
- Dominant language
- SystemVerilog
- Stars
- 84
- Forks
- 18
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- No merged PRs in 30d
Description
> daveshah: UltraScale+ devices have all unused LUTs set to output 1 by default, to save power
> daveshah: this results in loads of extra set bits in the FASM
> daveshah: it might be nice to have a bit2fasm option that skips these
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