RFC: Creating a synthesis or PnR benchmark

[Ian Cutress](https://twitter.com/IanCutress) has expressed interest in adding something FPGA-related to his CPU benchmarking suite. Here's my idea: benchmark the PnR step of the design using a frozen version of NextPnR, a pre-synthesised design(s), and a constant seed. Would that be enough to ensure the execution workload is equal across different platforms? Also, any recommendations on which designs from [yosys-bench](https://github.com/YosysHQ/yosys-bench) to use? Dr Cutress said he would like a benchmark that takes 30 minutes or less on a quad-core machine. I'm planning on running a Boom core or a LiteX SoC design through to see how long it takes next time I get a chance to.